The present invention relates to a semiconductor memory device having a redundancy circuit for rescuing failed memory cells, which is used in, e.g., a DRAM (dynamic memory).
FIG. 1 is a block diagram of a DRAM using an overlaid DQ scheme.
As shown in FIG. 1, in the DRAM using the overlaid DQ scheme, complementary data lines DQ and BDQ (to be referred to as data line pairs or pairs of data lines in this specification) run on a memory cell array/sense amplifier region 1 and a column selector region 2 in a direction parallel to complementary bit lines BL and BBL (to be referred to as bit line pairs or pairs of bit lines in this specification).
FIG. 1 shows two pairs of data lines DQ1 and BDQ1, and DQ2 and BDQ2.
A plurality of pairs (eight pairs in FIG. 1) of bit lines BL1 and BBL1 to BL8 and BBL8 are commonly connected to the pair of data lines DQ1 and BDQ1 via column selection transistors CQ1-1 to CQ8-1.
Similarly, a plurality of pairs (eight pairs in FIG. 1) of bit lines BL9 and BBL9 to BL16 to BBL16 are commonly connected to the pair of data lines DQ2 and BDQ2 via column selection transistors CQ1-2 and CQ8-2.
The gates of the column selection transistors CQ1-1 and CQ1-2 are connected to a column selection line CSL1, the gates of the column selection transistors CQ2-1 and CQ2-2 to a column selection line CSL2, . . . , and the gates of the column selection transistors CQ8-1 and CQ8-2 to a column selection line CSL8, respectively. These column selection transistors CQ1-1 to CQ8-1 and CQ1-2 to CQ8-2 are turned on/off in correspondence with the potentials on the column selection lines CSL1 to CSL8.
In such DRAM, a column including a failed memory cell is normally rescued by replacing it by a redundant column together with a pair of data lines DQ and BDQ.
More specifically, as shown in FIG. 1, a pair of redundant data lines RDQ and RBDQ run in addition to the pair of regular data lines DQ and BDQ. Eight pairs of redundant bit lines RBL1 and BRBL1 to RBL8 and BRBL8 are commonly connected to the pair of redundant data lines RDQ and BRDQ via redundant column selection transistors RCQ1 to RCQ8.
The gate of the redundant column selection transistor RCQ1 is connected to the column selection line CSL1, the gate of the redundant column selection transistor RCQ2 to the column selection line CSL2, . . . , and the gate of the redundant column selection transistor RCQ8 to the column selection line CSL8, respectively. These redundant column selection transistors RCQ1 to RCQ8 are turned on/off in correspondence with the potentials on the column selection lines CSL1 to CSL8.
In the above-mentioned conventional DRAM, when a column including a failed memory cell is selected, a pair of redundant data lines RDQ and RBDQ are selected in place of the pair of regular data lines DQ and BDQ.
However, in the conventional DRAM, one of the pair of regular data lines DQ1 and BDQ1, and the pair of regular data lines DQ2 and BDQ2 can only be rescued.
In addition, in recent DRAMs, the number of pairs of bit lines BL and BBL connected to the pair of regular data lines DQ and BDQ increases, and the probability of failures in both the pairs of regular data lines DQ1 and BDQ1, and DQ2 and BDQ2 is very high. For this reason, the conventional DRAM has poor rescue efficiency.
In order to improve the rescue efficiency, the present applicant has proposed a rescue method of dividing the pairs of regular bit lines BL and BBL connected to the pair of regular data lines DQ and BDQ, and the pairs of redundant bit lines RBL and BRBL connected to the pair of redundant data lines RDQ and RBDQ into two groups, and rescuing a failed memory cell in units of groups (Japanese Patent Laid-Open No. 8-221998). FIG. 2 shows a DRAM using this rescue method.
The difference between the improved DRAM shown in FIG. 2 and the DRAM shown in FIG. 1 lies in that pairs of regular bit lines BL1 and BBL1 to BL8 and BBL8, pairs of regular bit lines BL9 and BBL9 to BL16 and BBL16, and the pairs of redundant bit lines RBL1 and BRBL1 to RBL8 and BRBL8 are respectively divided into two groups A and B each including four bit line pairs.
The pairs of redundant bit lines RBL1 and BRBL1 to RBL4 and BRBL4 (group A) are used for rescuing the pairs of regular bit lines BL1 and BBL1 to BL4 and BBL4, or BL9 and BBL9 to BL12 and BBL12.
On the other hand, the pairs of redundant bit lines RBL5 and BRBL5 to RBL8 and BRBL8 (group B) are used for rescuing the pairs of regular bit lines BL5 and BBL5 to BL8 and BBL8, or BL13 and BBL13 to BL16 and BBL16.
In this improved DRAM, even when failures have been produced in both the pairs of regular data lines DQ1 and BDQ1, and DQ2 and BDQ2, they can be rescued if failed memory cells are separately present in groups A and B.
However, in the improved DRAM, the column selection lines CSL1 to CSL8 are shared by the pairs of redundant bit lines RBL1 and BRBL1 to RBL8 and BRBL8, and the pairs of regular bit lines BL1 and BBL1 to BL16 and BBL16, as in the DRAM shown in FIG. 1.
For this reason, if failed memory cells are present in an identical group, rescue cannot be done.
As described above, even in the improved DRAM, an unrescuable case often takes place, and the rescue efficiency is not always improved.